Read Only Memory (ROM) are commonly used to store programs in computer systems. Although mask-programmed ROMs are the least expensive when manufactured in high volume, they have the disadvantages of high initial design cost and long lead time to manufacturing. Programmable ROMs (PROMs), of which there are many types, have the advantage of being field programmable.
Bipolar PROMs, which incorporate bipolar fusible links or vertical shorting junction elements, have typically been used for high-speed applications, despite their relatively high manufacturing cost, high power consumption, and low circuit density. Fusible links are particularly problematic. Not only are high current values required to blow the fusible links during programming, but the photolithographic and etch steps required for their formation must be precisely controlled so as to minimize process variability. Unless link size and shape is controlled within a narrow range, it will not function effectively both as a conductor if not blown and as a completely open circuit if blown.
Where speed is not of paramount importance, electrically-programmable ROMs (EPROMs) employing floating gate technology have been typically employed. Such EPROMs feature greater circuit density than bipolar EPROMs, due to a more compact cell design. However, the manufacture of floating gate EPROMs requires complicated processing. Additionally, data is retained in the floating gate, which is vulnerable to leakage and ultraviolet radiation, either of which may result in the permanent loss of data.
Various other PROM cells have been proposed that utilize antifuse elements for the programmable link. Generally, the antifuse elements are essentially capacitors, consisting of two conductive or semiconductive materials separated by a dielectric layer. During programming, the dielectric layer is broken down by the application of a programming voltage that is significantly greater than the normal read voltage, thereby electrically connecting the conducting materials.
For the PROM cells described in U.S. Pat. Nos. 3,634,929 and 4,499,557, an isolated diode is used as the selection element and a capacitor is used as the programmable antifuse element. Such designs suffer from several disadvantages. Reverse bias leakage will result in high background current values. In addition, the programming operation tends to stress the dielectric on cells which are to remain unshorted. Finally, it is difficult to balance the need to utilize a read voltage which will be sufficient to trigger the column sense amps without exerting undue stress on the dielectric of the unshorted cells during the useful life of the device.
The PROM cells described in U.S. Pat. Nos. 4,322,822 and 4,507,757 utilize a programmable antifuse capacitor in combination with a MOS transistor, which functions as the selection element. The first referenced patent discloses an electrically-programmable memory array having capacitor devices formed in anisotropically etched V-grooves, which provide enhanced dielectric breakdown at the apex of the groove. After breakdown (i.e., programming), a cell exhibits a low resistance to a grounded substrate. This cell structure is somewhat difficult to manufacture, in that it requires a highly-conductive, grounded substrate. Additionally, the design does not lend itself to high density circuit layout. The second referenced patent ('757) discloses an electrically-programmable memory array having a thin-oxide avalanche fuse element which is programmed at voltage below the oxide breakdown level. Such a design is extremely susceptible to manufacturing process variability, since the avalanche phenomenon is difficult to control.